The present invention relates generally to the field of semiconductor technology, and more particularly to through silicon via formation in semiconductor manufacture.
There continues to be a demand for more densely formed integrated circuits on semiconductor chips. One approach has been to reduce the physical scale of the circuit components so more circuits can be formed laterally on a semiconductor chip. Another approach is to vertically form devices on a semiconductor chip such as a vertical field effect transistor (VFET) or a three dimensional device structure such as a finFET. Silicon on insulator (SOI) structures provide another opportunity for vertical integration of semiconductor devices. A SOI structure for a SOI wafer has an insulating layer that may be grown in a semiconductor wafer or alternatively, a SOI wafer is composed of two semiconductor wafers bonded together, one of which has an insulating layer on a wafer top surface. The insulating layer on the top surface of the one wafer is sandwiched between the two semiconductor wafers when bonded. While another approach for vertical integration is to integrate two or more chips, each having semiconductor devices and interconnect wiring using three dimensional (3D) chip to chip stacking technology. Some of the advantages provided by 3D stacking include enabling a greater density of integrated circuits, enhanced performance, and improved form factors. There are a number of applications for 3D stacking including high performance devices, video and graphics processors, and high density, high bandwidth memory chips.
3D structures and silicon on insulator (SOI) structures employ through silicon vias (TSV) to provide electrical connections between the semiconductor devices and to the interconnect wiring formed on the multiple semiconductor wafer or chip layers. Preferably, a TSV has high conductivity and uses high conductivity materials such as copper, tungsten and less commonly, polysilicon to fill vias. Since TSV by definition extends through the semiconductor wafer, a TSV length is approximately the thickness of the semiconductor chip or wafer, which can be orders of magnitude more than a typical back end of line (BEOL) interconnect via length connecting only a few BEOL interconnect layers of a semiconductor wafer. Typically, TSVs extend from a metal-line level wiring layer in the BEOL interconnect to a bottom surface of the semiconductor chip.